Adders are one of the widely used digital components in digital integrated circuit design. Addition is the basic operation used in almost all computational systems. Therefore, the efficient implementation and design of arithmetic units requires the binary adder structures to be implemented in an equally efficient manner. A ripple carry adder has smaller area but less speed. A carry look-ahead adder is faster though its area requirements are high. Carry select adders (CSLA) lie in middle. In this work a novel carry select adder using Binary Excess Converter (BEC) is proposed. It provides good compromise between cost and performance thereby establishing a proper trade-off between time and area complexities. In this work Tanner EDA is used for the comparison of all adders – Ripple carry adder, Bitwise carry select adder, Square root carry select adder, proposed carry select adder using BEC.
Inhaltsverzeichnis
- Introduction
- Regular Carry Select Adder
- Binary Excess Convertor (BEC)
- Proposed Carry Select Adder
- Results
- Conclusion
- References
Zielsetzung und Themenschwerpunkte
This paper proposes a novel carry select adder (CSLA) using a Binary Excess Converter (BEC) to improve the performance of adders in digital integrated circuits. The objective is to achieve a balance between cost and performance, reducing area and power consumption while maintaining speed. The paper compares the proposed design with existing adders, including ripple carry adders, bitwise carry select adders, and square root carry select adders.
- High-speed adder design
- Area and power optimization
- Carry select adder architecture
- Binary Excess Converter (BEC) implementation
- Performance comparison with existing adders
Zusammenfassung der Kapitel
The introduction discusses the increasing demand for high-speed arithmetic units in various applications and the need for efficient adder designs. It highlights the limitations of ripple carry adders and introduces the carry select adder (CSLA) as a faster alternative.
The chapter on regular carry select adders explains the basic architecture and its advantages in reducing propagation delay. It also mentions different logic styles that can be used for optimization.
The chapter on Binary Excess Convertor (BEC) describes the BEC logic diagram and its advantages in terms of reduced gate count compared to full adders. It also includes a schematic view and waveform of the BEC.
The chapter on the proposed carry select adder presents the architecture of the modified CSLA, which replaces the RCA with BEC. It explains how this modification reduces area and power consumption while maintaining speed. The chapter also includes simulation results and a comparison with the regular SQRT CSLA.
The results section presents a table comparing the area, delay, and power consumption of the regular and modified CSLA. It highlights the significant reduction in area and power achieved by the proposed design.
Schlüsselwörter
The keywords and focus themes of the text include carry select adder, binary excess converter, fast adder, area optimization, power reduction, VLSI design, digital circuits, and high-speed arithmetic units.
- Citation du texte
- Prajakta Wasekar (Auteur), Prof. U.M. Gokhale (Auteur), 2012, High Performance Carry Select Adder Using Binary Excess Converter, Munich, GRIN Verlag, https://www.grin.com/document/288145
