Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow.
The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes.
The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment.
The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing.
Inhaltsverzeichnis (Table of Contents)
- Abstract
- Introduction
- Chapter 1: Mixed Selected Selective Huffman and Run Length Coding Techniques Algorithm (SSHRLC)
- Chapter 2: Combined Compatible Block and Run Length Coding Algorithm (CCBRLC)
- Chapter 3: Modified Run Length Coding Technique Based On Multi-Level Selective Huffman Coding Algorithm (MRLMHC)
- Chapter 4: Hybrid of Bitmask Dictionary and 2" Pattern Run Length Coding Algorithm (BDPRLC)
- Conclusion
Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)
The objective of this research is to improve test data compression and decompression techniques for VLSI circuits, aiming to reduce test data volume and enhance testing efficiency. This is achieved by exploring and combining various code-based schemes to optimize compression ratios.
- Test data compression for VLSI circuits
- Comparison of different code-based compression algorithms
- Optimization of compression ratio
- Implementation and validation using MATLAB and VHDL
- VLSI implementation and analysis of design parameters
Zusammenfassung der Kapitel (Chapter Summaries)
Chapter 1: Mixed Selected Selective Huffman and Run Length Coding Techniques Algorithm (SSHRLC): This chapter introduces a novel compression algorithm, SSHRLC, which combines selected selective coding and run-length coding. By leveraging "don't care" and redundant bits within the test set, SSHRLC aims to improve compression ratios. The algorithm's implementation in MATLAB, its time complexity analysis using ISCAS benchmark circuits, and the achieved average compression ratio of 58% are presented and compared to existing methods. The lossless nature of the compression is validated through successful decompression and verification against the original test sets. The focus is on demonstrating the effectiveness of the combined approach in reducing test data volume for improved testing efficiency.
Chapter 2: Combined Compatible Block and Run Length Coding Algorithm (CCBRLC): This chapter proposes CCBRLC, another compression algorithm designed to reduce test data volume. The core concepts involve identifying and replacing compatible and incompatible blocks, using symbol representation and frequency analysis to achieve higher compression. The algorithm's MATLAB implementation and experimental results using ISCAS benchmark circuits are presented, along with comparisons to both existing methods and the previously presented SSHRLC algorithm. The chapter highlights the improved average compression ratio of 71%, showcasing the efficacy of the CCBRLC algorithm in minimizing test data while guaranteeing lossless recovery of the original test vectors. The preservation of testing performance is emphasized as a critical achievement.
Chapter 3: Modified Run Length Coding Technique Based On Multi-Level Selective Huffman Coding Algorithm (MRLMHC): Chapter 3 details the MRLMHC algorithm, a hybrid approach that combines a modified run-length coding (RLC) technique with multi-level selective Huffman coding. The algorithm leverages the most frequent sequences identified by the modified RLC and a limited set of selective Huffman codewords for enhanced compression. The chapter outlines the MATLAB implementation, experiments using ISCAS benchmark circuits, and performance comparisons against prior algorithms (SSHRLC and CCBRLC). The achieved average compression ratio of 77% is presented, indicating a further improvement. Additionally, the VHDL implementation for circuit s208, along with VLSI design parameters (power, area, propagation delay) obtained using Cadence EDA tools, demonstrate the feasibility of the algorithm's integration into a BIST environment.
Chapter 4: Hybrid of Bitmask Dictionary and 2" Pattern Run Length Coding Algorithm (BDPRLC): This chapter introduces BDPRLC, another hybrid compression algorithm combining bitmask dictionary and 2" pattern run-length coding. The algorithm's performance is analyzed using both MATLAB and VHDL implementations, with results compared to individual implementations of its component algorithms. The chapter emphasizes the synergistic benefits of the hybrid approach, resulting in a 12% improvement in compression ratio compared to the individual components. A detailed comparison with existing and previously proposed methods (SSHRLC, CCBRLC, MRLMHC) demonstrates that BDPRLC achieves the highest average compression ratio (86%) across most benchmark circuits. The chapter concludes by presenting the VHDL implementation and VLSI synthesis results for circuit s208, showcasing the algorithm's suitability for BIST environments and minimizing design parameters like area and propagation delay.
Schlüsselwörter (Keywords)
Test data compression, VLSI circuits, code-based compression, Huffman coding, run-length coding, BIST (Built-In Self-Test), compression ratio, MATLAB, VHDL, VLSI design parameters, ISCAS benchmark circuits, hybrid algorithms, lossless compression.
Frequently Asked Questions: A Comprehensive Preview of Test Data Compression Techniques for VLSI Circuits
What is the main objective of this research?
The primary goal is to enhance test data compression and decompression methods for VLSI circuits. This involves minimizing test data volume and improving testing efficiency by exploring and combining various code-based compression schemes to achieve optimal compression ratios.
What are the key themes explored in this research?
The research focuses on test data compression for VLSI circuits, comparing different code-based compression algorithms, optimizing compression ratios, implementing and validating algorithms using MATLAB and VHDL, and finally, analyzing VLSI implementation and design parameters.
What compression algorithms are presented and compared?
The research introduces and compares four novel algorithms: Mixed Selected Selective Huffman and Run Length Coding Techniques Algorithm (SSHRLC), Combined Compatible Block and Run Length Coding Algorithm (CCBRLC), Modified Run Length Coding Technique Based On Multi-Level Selective Huffman Coding Algorithm (MRLMHC), and Hybrid of Bitmask Dictionary and 2" Pattern Run Length Coding Algorithm (BDPRLC). Each algorithm's performance is evaluated and compared against existing methods and other algorithms presented in the research.
What are the chapter summaries?
Chapter 1 (SSHRLC): Introduces SSHRLC, combining selective coding and run-length coding to improve compression ratios. MATLAB implementation, time complexity analysis, and a 58% average compression ratio are presented.
Chapter 2 (CCBRLC): Presents CCBRLC, focusing on compatible/incompatible block replacement. MATLAB implementation, experimental results, and a 71% average compression ratio are detailed.
Chapter 3 (MRLMHC): Describes MRLMHC, a hybrid approach using modified run-length coding and multi-level selective Huffman coding. MATLAB and VHDL implementations, a 77% average compression ratio, and VLSI design parameters are provided.
Chapter 4 (BDPRLC): Introduces BDPRLC, a hybrid algorithm combining bitmask dictionary and 2" pattern run-length coding. MATLAB and VHDL implementations, achieving the highest average compression ratio (86%), and VLSI synthesis results are presented.
What tools and benchmarks were used for implementation and validation?
MATLAB and VHDL were used for algorithm implementation and validation. ISCAS benchmark circuits served as test cases for evaluating algorithm performance. Cadence EDA tools were employed for VLSI synthesis and analysis in Chapter 3 and 4.
What are the achieved compression ratios for each algorithm?
SSHRLC achieved an average compression ratio of 58%. CCBRLC achieved 71%. MRLMHC achieved 77%. BDPRLC achieved the highest average compression ratio at 86% across most benchmark circuits.
What are the key takeaways of this research?
This research demonstrates the effectiveness of hybrid compression algorithms in achieving significantly improved compression ratios for VLSI test data. The findings highlight the potential for reducing test data volume and enhancing testing efficiency, with implications for BIST (Built-In Self-Test) environments and minimizing VLSI design parameters (power, area, propagation delay).
What are the key words associated with this research?
Test data compression, VLSI circuits, code-based compression, Huffman coding, run-length coding, BIST, compression ratio, MATLAB, VHDL, VLSI design parameters, ISCAS benchmark circuits, hybrid algorithms, lossless compression.
- Quote paper
- Dr. Kalamani Chinnappa Gounder (Author), 2018, Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits, Munich, GRIN Verlag, https://www.grin.com/document/430834
