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Low Power Dissipation in VLSI Circuits. A Study of Low Power VLSI Design Techniques

Term Paper, 2023

14 Pages, Grade: A

Dr. Arpita Patel (Author)

Abstract or Introduction

This book will discuss contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life.

Details

Title: Low Power Dissipation in VLSI Circuits. A Study of Low Power VLSI Design Techniques
Grade: A
Authors: Dr. Arpita Patel (Author)Dr. JIgar Sarda (Author)
Year: 2023
Pages: 14
Catalog Number: V1394101
ISBN (eBook): 9783346949653
ISBN (Book): 9783346949660
Language: English
Keywords: Low power, Stratagies, Power Dissipation

Quote paper: Dr. Arpita Patel (Author)Dr. JIgar Sarda (Author), 2023, Low Power Dissipation in VLSI Circuits. A Study of Low Power VLSI Design Techniques, Munich, GRIN Verlag, https://www.grin.com/document/1394101

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